The present application claims priority upon Japanese Patent Application No. 2001-273932 filed on Sep. 10, 2001, which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to a storage control device which connects to a host processing device through a full-duplex channel and which stores data received through the channel in a data-storage means, and more particularly, to a technique for efficiently utilizing the above-mentioned channel.
2. Description of the Related Art
Fibre Channel Protocol (referred to hereinafter as “Fibre Channel”) is known as a communication protocol for connecting a host processing device, such as a mainframe, and a storage control device, such as a disk array device. Reference should be made to FC-PH (Fibre Channel Physical and Signaling Interface) of ANSI (American National Standard for Information Technology) for details.
Fibre Channel is basically configured to have a physical connection between two ports. A pair of Fibre Channel ports is mutually connected physically via two channels for transmit/receive (i.e., a full-duplex channel). The communication in Fibre Channel, conducted between the storage control device and the host processing device through this channel, is carried out based on a data unit called a “frame”. A bundle of a plurality of frames is called a “sequence”, and a bundle of a plurality of sequences is called an “exchange”. For example, a series of processes, corresponding to a data-read-out instruction (Read instruction) conducted from a host processing device to a storage control device, is carried out on an exchange-by-exchange basis. Further, in communication between the host processing device and the storage control device in Fibre Channel, it is possible to transmit/receive commands and/or frames without interlocking.
FIG. 1 shows an example of a data-processing system structured to comprise a storage control device 10 connected to a channel of Fibre Channel, and a host processing device 20 using the above. The storage control device 10 is, for example, a disk array device comprised mainly of a cache memory 11, a data storage means 12 such as disk units, and CPUs, memories and so forth. The storage control device 10 also comprises a channel controlling section 14 which, for example, conducts data communication with the host processing device 20, assigns data to be the object of processing to channel processors 13, manages various data and tables, and/or manages queues for various instructions to the channel processors 13; and comprises the channel processors 13 which divide the frames received from the channel controlling section 14, and execute processes corresponding to each of the frames and data-transmission control to the data storage means 12 via the cache memory 11. Here, the host processing device 20 is, for example, a mainframe, an office computer or a personal computer.
In communication between the storage control device 10 and the host processing device 20, the storage control device 10 assigns a channel processor 13 for processing each of the frames in the order of receipt of the frames. Here, in case the channel processor 13 is in use, the channel processor 13 not in use will be assigned for processing of the frame.
The commands contained in a frame sent from the host processing device 20 to the storage control device 10 is broadly classified mainly into a WRITE command for instructing data write-in to the data storage means 12, and a READ command for instructing read-out. In conducting processes corresponding to these commands, there sometimes occurs a period in which both of the plurality of channel processors 13 are only processing either one of the WRITE command or the READ command at the same time, in a case where frames, containing only either one of the WRITE command or the READ command, are successively sent from the host processing device 20, or, for reasons such as that data amount to be the object of write-in or read-out is large. During such a period, the full-duplex communication will not effectively function.
That is, for example, in case there are only two channel processors 13 in the structure, although the communication load is heavy only in channel 51 in the direction from the host processing device 20 to the storage control device 10 among the above-mentioned full-duplex channel (hereinafter referred to as “receiving channel”), the channel 52, in the direction from the storage control device 10 to the host processing device 20, (hereinafter referred to as “transmitting channel”) is nearly unused. Thus, during such a period, the full-duplex channel 50 will not function effectively.